Image sensor, camera system comprising the image sensor and method of manufacturing such a device

ABSTRACT

An image sensor ( 1 ) having a semiconductor body ( 2 ) with a first conductivity type and having a surface ( 3 ), the surface being provided with a number of cells ( 4 ), a cell comprising a photosensitive element ( 5 ) and a reset transistor ( 6 ), the reset transistor comprising a source region ( 7 ), a drain region ( 8 ) and a gate region ( 9 ), the source region ( 7 ) and the drain region ( 8 ) having a second conductivity type opposite to the first conductivity type, the source region ( 7 ) of the reset transistor ( 6 ) being electrically connected to the photosensitive element ( 5 ). There is a well region ( 10 ) present which well region extends from the surface ( 3 ) into the semiconductor body ( 2 ) and extends at least partly below the gate region ( 9 ) and the well region has a first conductivity type. The source region ( 7 ) extends at least substantially in a doped region ( 11 ) of the photosensitive element ( 5 ), the doped region ( 11 ) having a second conductivity type. The reduction of the source-well junction area reduced the number of white pixels and fixed pattern noise. In the method of manufacturing the image sensor, the well region ( 10 ) is positioned partly below the gate region ( 9 ) so that there is a distance ( 13 ) between the highly doped source region ( 7 ) and the well region ( 10 ). The distance ( 13 ) increases the depletion layer width between the source and well junction, so that tunnel currents no longer dominate the leakage currents and the related number of white pixels and fixed pattern noise are reduced.

The invention relates to an image sensor comprising a semiconductor bodyhaving a first conductivity type and having a surface, the surface beingprovided with a number of cells, a cell comprising a photosensitiveelement and a reset transistor, the reset transistor comprising a sourceregion, a drain region and a gate region, the source region and thedrain region having a second conductivity type opposite to the first,the source region of the reset transistor being electrically connectedto the photosensitive element.

The invention further relates to a camera system comprising the imagesensor.

The invention also relates to a method of manufacturing a CMOS imagesensor comprising the steps of:

-   -   forming a photosensitive element in a semiconductor substrate        having a first conductivity type by providing dopant atoms into        a region in the semiconductor substrate, the dopant atoms having        a second conductivity type in the region opposite to the first        conductivity type,    -   using a protection mask over the region of the photosensitive        element after which a well region is formed by implanting ions        having a first conductivity type in the semiconductor substrate,    -   forming a gate region by depositing a layer of gate material and        patterning the layer.

U.S. Pat. No. 6,177,293 discloses a method for forming a CMOS imagesensor that minimizes the occurrence of white pixels in images. In themethod, field oxide surrounding the photosensitive region of a cell isformed with interior angles greater than 90 degrees and/or iscontinuously curved. In this way mechanical and electrical stress in thefield oxide surrounding the photosensitive region of the cell isminimized. Regions subjected to excessive mechanical stress duringfabrication, and regions subjected to excessive electrical stress duringdevice operation show excessive current leakage. In order to be lesssensitive to these regions subjected to stress, the reset gate has anoffset from the photosensitive regions of active pixel cells by adistance greater than 0.25 μm.

It has been determined that excessive current leakage from thephotosensitive (e.g., photodiode) regions is a significant cause ofwhite pixel problems in CMOS image sensors.

It is a problem that despite the measures indicated above, there arestill large numbers of white pixels in CMOS image sensors. White pointdefects or spots visible on the display or monitor are the result of alocal charge carrier generation site that in all cases causes additionalcharge carriers in the charge packet integrated near it.

Moreover, the variance in dark current between the pixels in the image,called fixed pattern noise, is a major problem. The dark currentgeneration is hardly uniform from cell to cell. The generation centersof the dark current are statistically distributed through thesemiconductor. This means that not all cells have the same number ofgeneration centers. On the other hand the generation rate of each centercan also vary from type to type. All these variations make the darkcurrent no longer uniform. Non-uniform dark-current generation addsfixed pattern noise to the signal. Fixed pattern noise is very hard toremove. This is only possible if the distribution of this non-uniformspurious signal is known.

The invention has for its object to provide an image sensor of the typementioned above, having a reduced number of white pixels and a reducedfixed pattern noise.

To achieve the object, the image sensor according to the invention ischaracterized in that a well region is present which well region extendsfrom the surface into the semiconductor body and extends at least partlybelow the gate region and the well region having a first conductivitytype, the source region extending at least substantially in a dopedregion of the photosensitive element, the doped region having a secondconductivity type.

A significant contribution to white pixels and fixed pattern noise (FPN)originates from the source diffusion of the MOS field effect transistor(MOSFET) connected to the photosensitive element. The invention is basedon the insight that the white pixels and fixed pattern noise are mainlycaused by the source-well junction. This junction causes large leakagecurrents due to tunneling of charge carriers through the depletionlayer. The tunnel current can be a trap assisted tunnel current or adirect tunnel current. Leakage currents due to tunneling in thesource-well junction can be distinguished from regular Shockly-Read-Hallrecombination by the exponential behavior of the current as a functionof the voltage applied across the junction. A correlation has been foundbetween the exponential behavior of the leakage current in thesource-well junction, the number of white pixels and the fixed patternnoise.

By positioning the source region substantially in the doped region ofthe photosensitive element, the source-well junction area is reduced andtherefore the number of white pixels and FPN are reduced. The leakagecurrent due to the junction between the source-photosensitive element isalmost negligible because the source region and the doped region of thephotosensitive element have the same conductivity type.

Preferably, the concentration of dopant atoms of the semiconductor bodyis present below the source. The relatively low concentration of thesemiconductor body forms a junction with the bottom area of the source.The width of the depletion layer is large, mainly extending in thesemiconductor body. The contribution of leakage current resulting inwhite pixels and FPN from this bottom area is negligible.

It is very advantageous to position the side-wall of the well at acertain distance from the source to reduce significantly the tunnelingcurrents. This can be explained because the separation distance betweenthe source and the well increases the depletion layer width. In fact theincrease in depletion layer width is roughly equal to the separationdistance. Because of the larger depletion width, the number of whitepixels and the fixed pattern noise decreases. It is desirable to have awell at the drain side. The well reduces short channel effects, draininduced barrier lowering and punch through.

It is very advantageous to position the side-wall of the well under thegate. The laterally out-diffused region of the well has a lower dopantconcentration than in the center of the well. Due to this lower dopantconcentration, the depletion layer width between the source and the wellbecomes larger and extends more in the well. The peak of the electricalfield is reduced as well as the gradient in the electrical field in thewell. The lower dopant concentration in the source side of the wellcauses a higher absolute value of the threshold voltage. This increasein the absolute value of the threshold voltage can be compensated with alonger gate length.

In contradiction to what has been found in the prior art, it isadvantageous to position the gate along the edge of the photosensitiveelement so that the source region extends entirely into the doped regionof the photosensitive element. In that case the source-well junctionarea is minimized. By doing this, all charge is effectively gathered inthe source and can easily be transported by putting a voltage on thegate of the reset transistor to form a channel. The well extends from anedge of the photosensitive element in the outer direction andcontributes to the depletion layer of the photosensitive element. Whenlight falls on the photosensitive element, electron-hole pairs aregenerated. Due to the electrical field in the depletion layer, theelectron-holes pairs are separated in the depletion layer of thephotosensitive element. The charge carriers of the second conductivitytype, e.g. electrons, are accelerated in the direction of the highlydoped source. As long as the reset transistor is closed, charge isgathered on the source. After some time, for instance 10 ms, a voltageis set on the gate and the reset transistor opens. The charge can easilybe transported through the channel of the reset transistor.

Two different types of sensors can be realized in CMOS technology. Theseare passive and active pixel sensors (APS). The difference between thesetwo types is that a passive pixel does not perform signal amplificationwhereas an active pixel does. A passive pixel sensor is simply aphotodiode (MOS or p-n junction diode) with a transistor that passesphotoelectrically generated signal charge to an amplifier outside thepixel array. In an active pixel, the integrated charge is amplified by asource follower transistor and transported in the channel of the resettransistor. The gate of the source follower transistor is connected tothe source of the reset transistor.

When the length of the gate of the reset transistor is the same as thelength of the gate of the source follower, the absolute value of thethreshold voltage of the reset transistor will be lower than for thesource follower transistor. The well of the reset transistor is onlypartly present below the gate of the reset transistor, so that theconcentration of the dopant atoms is lower than below the gate of thesource follower transistor. In order to compensate the lower absolutevalue of the threshold voltage of the reset transistor, the length ofthe gate of the reset transistor is increased. So it is advantageous todesign the length of the gate of the reset transistor longer than thelength of the gate of the source follower transistor.

The active pixel image sensor may be part of a camera system, forexample a Digital Still Camera, a webcam, a video camera recorder(camcorders), or a mobile application such as a cellular phone.

It is further an object of the method of the kind mentioned above toreduce the number of white pixels and the fixed pattern noise withoutusing additional mask steps in a standard CMOS process.

To achieve the object, the method of manufacturing the image sensoraccording to the invention is characterized in that the gate region isformed over a side-wall of the well region, the side-wall being presentbetween the region of the photosensitive element and the well region.

The invention is further based on the insight that the implantation ofions of the second conductivity type, forming the photosensitiveelement, introduces end of range damage in the semiconductor substrateand metal atoms. These metal atoms like Fe, Au, Pt are traps in thebandgap of the semiconductor substrate. If the metal atoms are locatedin the depletion layer between the implanted region forming thephotosensitive element and the well, then they can be responsible for atrap assisted tunneling current. Electrons can tunnel to the trap,recombine with a hole, giving rise to a larger number of white spots anda larger fixed pattern noise. The trap assisted tunneling currentincreases when there is a voltage applied over the depletion layer.

In order to circumvent this trap assisted tunnel current, the gate isformed over a side-wall of the well. The well is retracted over adistance relative to the gate length. Now there is a separation distancebetween the implanted region of the photosensitive element and the well.Due to this separation distance, the depletion layer is so large thatonly Shockley Read Hall recombination can take place and trap assistedtunneling currents no longer contribute. Moreover, the depletion layeris formed between the implanted region and the semiconductor substrate,having a lower dopant concentration than the well. Therefore, theleakage current is reduced, resulting in a reduced number of white spotsand a reduced fixed pattern noise.

Preferably the source region is formed self-aligned to the gate and ispositioned at least substantially in the implanted region of thephotosensitive element. Because the source has the same conductivitytype as the photosensitive elements, the leakage currents are almostnegligible.

Usually a source region and a drain region is formed by implanting ionsof a second conductivity type self-aligned to the gate. It is veryadvantageous when there is a distance between the source and the well.The source is highly doped. The source-well junction causes tunnelingcurrents. These tunneling currents can be trap assisted tunnelingcurrents or direct tunneling currents through the depletion layer. Thespacing reduces the dopant concentration and therefore increases thedepletion layer width. The distance between the source and the welleffectively increases the depletion layer width. The distance should bechosen such that the depletion width is too large at the operationvoltages for trap assisted tunneling currents to occur. In silicon trapassisted tunneling can occur when the depletion layer width is smallerthan about 40 nm. For direct tunneling the depletion layer should besmaller than about 25 nm.

It is advantageous when the field isolation is formed on thesemiconductor substrate and the photosensitive element is formed byimplantation of the ions of the second conductive type through the fieldisolation. The surface of the light sensitive element is no longer thesilicon substrate, but the bottom of the field isolation. The fieldisolation can be a silicon oxide formed in a LOCOS process. The numberof dangling bonds that is usually present at the surface of thesemiconductor surface can be reduced. Below the field oxide, the siliconforms SiO₂ bonds so that the leakage current can be reduce and theresult is a reduced number of white spots and fixed pattern noise.

The photosensitive element has an edge formed by the field isolation. Itis advantageous to position the gate along that edge so that the entiresource region is located in the implanted region forming thephotosensitive element. The source and the implanted region of thephotodiode have the same conductivity type. The leakage current betweenthe highly doped source region and the lower doped region is negligible.The bottom area of the source region of the reset transistor no longercontributes to the leakage current. Only the relative small side-wall ofthe source junction can contribute to the leakage current. The leakagecurrent is significantly reduced as well as the number of white pixelsand the fixed pattern noise.

These and other aspects of the invention will be apparent and elucidatedwith reference to the drawings described hereinafter.

FIG. 1 is a schematic diagram of a known image sensor;

FIG. 2 is an electrical circuit of a three-transistor cell of the knownimage sensor;

FIG. 3 is a schematic of the operation principle of a three-transistorcell.

FIG. 4 a is a first embodiment of the photosensitive element and thereset transistor in top view according to the invention;

FIG. 4 b is a cross-sectional view along the line A-A′ in FIG. 4 a.

FIG. 4 c is a cross-sectional view along the line B-B′ in FIG. 4 a.

FIG. 5 is the leakage current in the junction between the n+ source andthe p-well.

FIG. 6 is a distribution of the dark current of an image sensor having480×640 cells at elevated temperature.

FIG. 7 a is a second embodiment of the photosensitive element and thereset transistor in top view according to the invention.

FIG. 7 b is a cross sectional view along the line A-A′ in FIG. 7 a.

FIG. 8 a is a third embodiment of the photosensitive element and thereset transistor in top view according to the invention.

FIG. 8 b is a cross sectional view along the line A-A′ in FIG. 8 a.

FIG. 9 a is a fourth embodiment of the photosensitive element and thereset transistor in top view according to the invention.

FIG. 9 b is a cross sectional view along the line A-A′ in FIG. 9 a.

FIG. 10 shows a histogram of the number of white pixels correlated withthe leakage current for the different embodiments;

FIG. 11 is a method of manufacturing the image sensor according to theinvention;

FIG. 12 is a simulation of the dopant profiles of the differentembodiments.

Active pixel sensor (APS) imagers are usually realized as solid stateimagers in a Complementary Metal-Oxide Semiconductor (CMOS) integratedcircuit (IC) process. In normal use an APS imager may be part of acamera system, for example a Digital Still Camera, a webcam, a videocamera recorder (camcorders), or a mobile application such as a cellularphone.

The image sensor in FIG. 1 comprises a number of cells 4 arranged in atwo-dimensional pattern of horizontal rows and vertical columns. Thecells are connected in a vertical direction to readlines 30. Thereadlines 30 pass the signals to a read-out element 31. In thehorizontal direction the cells are connected to selection lines 32 viawhich selection signal can be sent to a row to be read out, which row isselected by addressing means 33. In the horizontal direction the cellscan also be connected by horizontal reset lines that are not shown inthe drawing.

The cells 4 are formed along the surface 3 of the semiconductor body 2,with each cell periodically generating a signal having a current orvoltage level that is indicative of the intensity of light incident tothat cell. A typical three-transistor cell that is used in current CMOSimage sensors is shown in FIG. 2. Sensors that use this technology areoften referred to as CMOS active pixel sensors (APS).

A timing diagram for the operation of the three-transistor cell 4 isshown in FIG. 3. In typical operation a node N1 is set to apredetermined Voltage Vdd′ (which may be different from the circuitoperating voltage Vdd) by turning on an n-channel reset transistor 6.The state of the reset transistor is determined by controlling a resetvoltage (Vreset). In FIG. 3, Vreset goes high at time T0, causing thenode N1 to ramp to Vdd′. At time T1, the reset transistor 6 is turnedoff and photoelectrons are generated by the incident light on aphotosensitive element in the form of a photodiode 5. The photoelectronsare injected into node N1, reducing the voltage on that node by a valueof Vsense=Vdd′−(I_(photo)×T_(illuminate)/C_(N1)). In this equationI_(photo) is the photocurrent induced by the incident light,T_(illuminate) is the illumination time period and C_(N1) is thecapacitance on node N1. Both Vdd′ and Vsense can in principle be readout of the pixel by a source follower transistor 16 by activating arow-select transistor 25. In a two-dimensional array of cells, theretypically are row-select transistors and column-select transistors thatallow the cells to be sequentially sampled. The row select transistor 25is activated by manipulating a row-select signal. The illumination onthe cell is then proportional toVdd′−Vsense=I_(photo)×T_(illuminate)/C_(N1). Persons skilled in the artrefer to this operation as Double Sampling. Sampling occurs at time T2before T_(illuminate) and time T3 during T_(illuminate). The cell isreset at time T4, since Vreset is caused to go high.

This sample technique can be used to remove several kinds of noise inhigh performance imaging systems. Double Sampling involves taking twosamples of a sensor output. First, a reference sample is taken thatincludes background noise and noise derived from a device mismatch. Thena second sample is taken of the background noise, device mismatch, andthe data signal. Subtracting the two samples removes any noise which iscommon (or correlated) to both, leaving only the data signal.

In silicon fabrication, an NMOS switching device with minimum size isnormally used as the reset transistor in order to obtain minimum pixelsize for good image resolution, and to minimize parasitic capacitances.

FIG. 4 a gives a top view of an advantageous first embodiment of thephotosensitive element 5 and the reset transistor 6 in the semiconductorbody 2 according to the invention. The semiconductor body is in thisembodiment a silicon substrate, but the semiconductor substrate is notlimited to silicon and can be e.g. Ge or GaAs. The p-type siliconsubstrate is provided with an n-well. The n-well forms with the p-typesubstrate the photosensitive element in the form of a photodiode 5. Thesource- and drain regions of the reset transistor, in this example ann-channel transistor, are formed by the n-type zones 7 respectively 8that are provided in the substrate.

There is a p-well region 10 present extending from the surface 3 intothe semiconductor body 2. In this embodiment the p-well region 10extends below the entire gate region 9. In deep-submicron CMOStransistors a well is necessary to reduce the sub-threshold voltageleakage current and compensate for short channel effects. Reversebiasing the back contact or bulk of a MOS transistor relative to thesource is a method that has been employed to adjust the thresholdpotential. This electrical method of adjustment makes use of theso-called body effect or substrate-bias effect. In essence, back biasingchanges the inversion point in the semiconductor from 2Φ_(F) to2Φ_(F)-V_(BS). Back-biasing always increases the absolute magnitude ofthe ideal device threshold voltage.

The tunneling currents can be reduced by decreasing the junction areabetween the n+-source 7 and the p-well 10. The junction between thep-well and the source is indicated with a thick dashed line. Then+-source area in the p-well is reduced by moving the gate of the resettransistor in the direction of the photodiode, as indicated with thearrow in FIG. 4 a and FIG. 4 b. The source region 7 extends at leastsubstantially in a n-type doped region 11 of the photosensitive element5. The junction between the n+-source and the n-well contributes to thedark current, but does not generate any tunneling currents.

In the cross-sectional view of FIG. 4 b the junction between the p-well10 and the source 7 is again indicated with a thick dashed line. Thetotal area of the junction between the p-well and the n-sourcedetermines largely the amount of tunnel currents. The dopantconcentration in the source is typical 10²⁰ at/cm³ As or P. The p-wellhas a peak boron concentration of typically a few times 10¹⁷ at/cm³.

The higher the dopant concentrations in the n-type source and thep-well, the smaller the depletion layer width. For the typical dopantconcentrations mentioned above, the depletion layer is about 46 nm. Ifthere is no voltage applied to the source, then there is onlyShockley-Read-Hall recombination in the depletion layer.

However, when a voltage is applied to the source (e.g. Vdd=3.3 V), theintrinsic electrical field increases in the source-well junction. Theincreased bending of the conduction and valence bands give rise to trapassisted tunneling currents. Most of the traps are metal atoms beingpresent in the bandgap of silicon. It is believed that the traps areintroduced during implantation steps.

An even further increase of the dopant concentration in the n−source orp-well can cause direct tunneling through the depletion layer.

The tunneling currents can be reduced by decreasing the junction areabetween the n−source and the p-well. The n+ source area in the p-well isreduced by moving the gate of the reset transistor in the direction ofthe photodiode, as indicated with the arrow in FIG. 4 b.

The junction between the n+ source and the n-well contributes to thedark current, but does not generate any tunneling currents.

In FIG. 5 the leakage current is measured for the first embodimenthaving a relatively large p-well-n+ source junction area of 0.5 μm×3 μm(curve a), and in the case that the junction area is reduced to 0.5μm×0.5 μm (curve b).

The reduction in leakage current is significant, especially at highervoltages, for example at 3V reverse bias.

It turned out that there is a clear correlation between the level andshape of the measured leakage current in the p-well-n+ source junctionand the detected number of white pixels and fixed pattern noise in thepixels.

In FIG. 6, a distribution of the fixed pattern noise of the pixels in a480×640 pixel image sensor is shown, measured at a temperature of 60degrees C. during an integration time of 330 ms. The integration time ischosen 10 times the normal integration time.

The measured output voltage shows a Gaussian distribution with a tail.When the output voltage is larger than 200 mV, the leakage current ofthe p-well-n+ source junction was high and showed an exponentialincrease above 3V.

When the output voltage is larger than 400 mV, the pixel is called awhite spot.

The found correlation between the leakage current in the p-well-n+source junction makes it possible to further reduce the number of whitespots and reduce the fixed pattern noise.

FIG. 7 a shows a second advantageous embodiment in which the leakagecurrent in the p-well-n source junction is reduced. In this example thep-well 10 is moved close to the gate 9 of the reset transistor. In thecross-sectional view of FIG. 7 b can be seen that the p-type substrate 2is present at the bottom 12 of the n+-source between the n-well 11 ofthe photodiode and the gate 9. The contribution of the n source-p-epilayer junction to the dark current is much less than for the n+source-p-well junction. The n+ source area in the p-well is reduced.

In a third very advantageous embodiment of FIG. 8 a the p-well 10 isaligned with the gate 9 and the entire n+-source 7 area is positioned inthe n-well 11 of the photodiode.

The p-well-n+ source junction area is reduced to only the periphery ofthe source at the gate side. This configuration has the disadvantagethat the threshold voltage of the MOST can change because the gate ispositioned at the side-wall 14 of the p-well 10. The p-well is formed byimplantation of boron and an anneal. The concentration of boron is nearthe side-wall 14 of the p-well 11 less than in the center of the p-well.The side-wall area of the p-well is formed by the laterally outdiffusedboron atoms. There is a gradient in dopant concentration at theside-wall area of the p-well. The lower dopant concentration at theside-wall area of the p-well reduces the threshold voltage V_(T).

The ΔV_(T) reduction in the threshold voltage of the reset transistorcan be compensated by an increase in the length 18 of the gate of thereset transistor.

The decrease of the threshold voltage in the NMOS reset transistor as afunction of gate length, called the V_(T) roll-off, can be easilymeasured. In the design, the gate length 18 of the reset transistor canbe adapted to exactly compensate for the ΔV_(T) due to the lower dopantconcentration at the edge of the p-well.

In a fourth embodiment of FIG. 9 the p-well 10 only extends partly belowthe gate 9. There is a distance 13 between the n+ source 7 and thep-well 10. Tunneling current in the n+-source-p-well junction area arecompletely eliminated.

In FIG. 10 a clear correlation is shown between the leakage current inthe n+-source-p-well diode and the relative number of white pixels inthe 480×640 pixel image sensor. The number of white pixels is determinedat a temperature of 60 degrees C. The reference situation is a resettransistor with a 0.5 μm gate length, a gate-photodiode distance of 1 μmand a substrate dopant concentration of 10¹⁴ at/cm³.

In the first embodiment the gate of the reset transistor is moved in thedirection of the photodiode over a distance of 0.15 m, 0.3 μm and 0.45μm.

In the second embodiment the p-well is shifted towards the reset gateover a distance of 0.15 μm and 0.3 μm.

In the third embodiment the length of the reset gate is increased with0.15 μm and 0.3 μm. The different variants in each embodiment areindicated in FIG. 10.

In the graph on top of the figure, the leakage current is shown in then+-source-p-well junction measured at a reverse bias of 4.5 V. A clearcorrelation can be seen between the amount of leakage current in then+-source-p-well junction and the relative number of white pixels shownin the histogram below. The lower the leakage current in eachembodiment, the lower the number of white pixels observed.

The best result concerning white pixels is found for the thirdembodiment, having a longer reset gate. From FIG. 10 it is clearly shownthat in all the embodiments the number of white pixels is significantlyreduced.

It has also been found that the leakage current measured at a reversebias (e.g. at 2.1V) shows a correlation with the width of the Gaussiandistribution of the dark current (see for instance FIG. 6). The fixedpattern noise therefore also depends on the source-p-well leakagecurrent.

In an advantageous method of manufacturing a CMOS image sensor a p-typesilicon substrate 40 is used. Field isolation regions 23 are formed witha poly buffered LOCOS process as shown in FIG. 11 a. In a resist mask 41openings are present through which P ions are implanted with a dose of10¹³ at/cm² at an energy of 500 keV. This implantation is identical tothe n-well implantation in the CMOS process. Through the same maskopenings an anti punch through implantation and a threshold voltageimplantation follow.

The resist mask is removed and a protection mask 22 is used covering then-well regions 11. The protection mask is in this embodiment a resistmask, having openings in order to implant a p-well as shown in FIG. 11b. The protection mask can also be a hard mask e.g. formed of siliconoxide or silicon nitride.

The p-well 10 is implanted with B ions with a dose of 6×10¹² at/cm² atan energy of 160 keV. The protection mask 22 is also used during theanti punch through implantation and the threshold voltage implantationin the p-well.

The protection mask 22 is removed and the dopant atoms are activated inan anneal in an oven. A thin thermal silicon oxide of 7.5 nm forms thegate oxide. Then a polysilicon layer is deposited and patterned, whichforms the gate region 9. In FIG. 11 c the gate length is 0.5 μm. Thelightly doped source and drain regions are formed self-aligned to thegate by implantation of As or P ions under an angle relative to thegate. A TEOS layer is deposited from which spacers are formed.

The heavily doped source and drain areas are implanted with As ions witha dose of 4×10¹⁵ at/cm² and an energy of 100 keV. After annealing, thesource and drain regions typically have a depth of 120 nm. The sourceregion 7 is at least substantially positioned in the n-well 11 of thephotodiode in order to reduce the n+ source-p-well junction area. Thereis a distance 13 between the source 7 and the p-well 10. The distance 13between the source 7 and p-well 10 largely determines the depletionlayer width.

In FIG. 11 d an alternative for step FIG. 11 a is shown, in which thephotosensitive element is formed almost entirely below the fieldisolation 23. The cross section is taken along the line A-A′ in FIG. 8 aThe photosensitive element 5 is formed by implantation of the ions ofthe second conductive type (e.g. As or P) through the field isolation23. The dashed lines of the LOCOS indicates the LOCOS seen at thebackground. There is a small active area formed in the LOCOS in whichlater the source region is formed. The position of the n-well below theLOCOS has the advantage that the dangling bonds, which are usuallypresent at the surface, form SiO₂ bonds so that the leakage current dueto dangling bonds can be reduced significantly. The leakage current caneven further be reduced with annealing in an atmosphere containinghydrogen in order to passivate the remaining dangling bonds.

In FIG. 11 e the n-type photosensitive element 5 has an edge 15 formedby the field oxide 23 (dashed LOCOS line at the background) and the gate9 is positioned along that edge. The source region 7 is entirely locatedin the n-well of the photodiode. This even further reduces the leakagecurrent. Usually the source region is made as small as possible, butsufficiently large to form a contact on this source region. The contactcan be a tungsten plug having a diameter of e.g. 0.4 μm.

The results after these manufacturing steps are shown in FIG. 12. Thedopant profiles are shown for the embodiments 1, 2 and 4 alreadydescribed here above.

In the first embodiment the distance between the gate region 9 and then-well 11 of the photodiode was 0.5 μm on the mask.

In the second embodiment the distance between the gate region 9 and then-well 11 of the photodiode was 0 μm on the mask.

In the fourth embodiment the gate region 9 only partly overlapped thep-well region 10. The distance between the edge of the gate and theside-wall 14 of the p-well was 0.3 μm on the mask (in the lengthdirection of the gate).

In the embodiments the junction between the source and the p-well isindicated with a white solid line. The concentration of As in the sourceis 10²⁰ at/cm³ and the concentration of boron in the p-well is about2×10¹⁷ at/cm³. Due to the distance 13 between the n+ source and thep-well in all embodiments, there is no overlap between the source andthe p-well. This greatly reduces the leakage current across the n+source and p-well junction.

1. An image sensor comprising a semiconductor body having a firstconductivity type and having a surface, the surface being provided witha number of cells, a cell comprising a photosensitive element and areset transistor, the reset transistor comprising a source region, adrain region and a gate region, the source region and the drain regionhaving a second conductivity type opposite to the first, the sourceregion of the reset transistor being electrically connected to thephotosensitive element, wherein a well region is present which wellregion extends from the surface into the semiconductor body and extendsat least partly below the gate region and the well region having a firstconductivity type, the source region extending at least substantially ina doped region of the photosensitive element, the doped region having asecond conductivity type.
 2. An image sensor as claimed in claim 1,wherein the source region has a bottom area being at least partlydelineated by the semiconductor body.
 3. An image sensor as claimed inclaim 1, wherein the drain region extends in the well region and adistance is present between the well region and the source region.
 4. Animage sensor as claimed in claim 3, wherein the gate region extends overa side-wall of the well region.
 5. An image sensor as claimed in claim1, wherein the gate is positioned along an edge of the photosensitiveelement.
 6. An image sensor as claimed in claim 5, wherein a sourcefollower transistor is present having a gate connected to the source ofthe reset transistor, the gate of the reset transistor having a lengthwhich is longer than the length of the gate of the source followertransistor.
 7. A camera system comprising the image sensor as claimed inclaim
 1. 8. A method of manufacturing a CMOS image sensor comprising thesteps of: forming a photosensitive element in a semiconductor substratehaving a first conductivity type by providing dopant atoms into a regionin the semiconductor substrate, the dopant atoms having a secondconductivity type in the region opposite to the first conductivity type,using a protection mask over the region of the photosensitive elementafter which a well region is formed by implanting ions having a firstconductivity type in the semiconductor substrate, forming a gate regionby depositing a layer of gate material and patterning the layer, whereinthe gate region is formed over a side-wall of the well region, theside-wall being present between the region of the photosensitive elementand the well region.
 9. A method as claimed in claim 8, wherein a sourceregion is formed by implanting ions of a second conductivity typeself-aligned to the gate, and the source region is at leastsubstantially formed in the region of the photosensitive element.
 10. Amethod as claimed in claim 8 or 9, wherein a distance is formed betweenthe source region and the well region.
 11. A method as claimed in claim8, wherein field isolation is formed on the semiconductor substrate andthe photosensitive element is formed by implantation of the ions of thesecond conductive type through the field isolation.
 12. A method asclaimed in claim 11, wherein the photosensitive element has an edgeformed by the field isolation and the gate is positioned along thatedge.